The present invention generally relates to integrated circuit memories, and more particularly to an automatically switching dual power rail cascode driver.
Miniaturization of field effect transistor (FET) devices has been advanced continuously for higher integration and higher performance of integrated circuits. It is known that the size of a FET is reduced according to the so-called “scaling law”. In the scaling law, a thickness of the FET's gate oxide film gets thinner as generations, i.e. technology nodes, change. For example, in the 14 nm technology node, the thickness of the gate oxide film is about 1.2 nm and the gate length is about 20 nm. A technology node area in this generation is approximately 196 nm2. In this technology node, an allowable voltage for a FET device may be approximately 0.8 V, for example. The term “allowable voltage” may refer to a voltage which is constantly or continuously applied to the FET without affecting its useful life.
Thin- and thick-oxide FETs may be exposed to regular (e.g., 0.8V) and high (e.g., 1.4V) voltages reliably in complementary-metal-oxide semiconductor (CMOS) technologies. At around the 14 nm technology node, the FET type was changed to fin from planar to scale further, as a result device manufacturing changed to only thin-oxide FETs. Due to thin-oxide FETs characteristics, long-term exposure to high voltages may cause damages to thin-oxide FETs, particularly to the gate dielectric and source/drain diffusion junctions, which may in turn reduce the life of thin-oxide FET devices.